Onur Kayıran's Homepage
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Onur Kayıran Email : onur.kayiran@amd.com |
About
I am an SMTS Design Engineer at AMD Research and Advanced Development.
I completed my Ph.D. studies in Department of Computer Science and Engineering
at The Pennsylvania State University, in 2015, where
I worked with Chita R. Das and
Mahmut T. Kandemir
in High Performance Computing Lab.
Research Interests
Broadly, my research interests are in the area of computer architecture. Specifically, I work in CPU archuarch, CPU vector processing, cachememory hierarchy and SoCs, GPU architectures, and die-stacking.
Publications
Onur Kayiran, Mohamed Ibrahim, Shaizeen Aga
Accelerating Ray Tracing via Processing in Memory,
In In-Memory Architectures and Computing Applications Workshop (iMACAW @ DAC 2023), San Francisco, CA, July 2023
Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, John Alsop, Paul Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William Brantley, Noel Chalmers, Shaoming Chen, Kevin Cheng, Michael L. Chu, David Cownie, Nicholas Curtis, Joris del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish Kotra, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliott Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Greg Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, Rene van Oostrum, Eric van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov, Varun Agrawal
A Research Retrospective on the AMD Exascale Computing Journey,
In the Proceedings of The 50th International Symposium on Computer Architecture (ISCA), Orlando, FL, June 2023
Mohamed Ibrahim, Onur Kayiran, Shaizeen Aga
Efficient Cache Utilization via Model-aware Data Placement for Recommendation Models,
In the Proceedings of The International Symposium on Memory Systems (MEMSYS), Virtual Event, September 2021
Mohamed Ibrahim, Onur Kayiran, Yasuko Eckert, Gabriel H. Loh, Adwait Jog
Analyzing and Leveraging Decoupled L1 Caches in GPUs,
In the Proceedings of The 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, South Korea, February 2021
(Acceptance rate: 63/258 = %24.4)
Mohamed Ibrahim, Onur Kayiran, Yasuko Eckert, Gabriel H. Loh, Adwait Jog
Analyzing and Leveraging Shared L1 Caches in GPUs,
In the Proceedings of The 29th International Conference on Parallel Architectures and Compilation Techniques (PACT), Atlanta, GA, October 2020
(Acceptance rate: 35/135 = %25.9)
Johnathan Alsop, Matthew D. Sinclair, Srikant Bharadwaj, Alexandru Dutu, Anthony Gutierrez, Onur Kayiran, Michael LeBeane, Sooraj Puthoor, Xianwei Zhang, Tsung Tai Yeh, Bradford M. Beckmann
Optimizing GPU Cache Policies for MI Workloads,
Short Paper in 2019 IEEE International Symposium on Workload Characterization (IISWC), Orlando, FL, November 2019
Mohamed Ibrahim, Hongyuan Liu, Onur Kayiran, Adwait Jog
Analyzing and Leveraging Remote-core Bandwidth for Enhanced Performance in GPUs,
In the Proceedings of The 28th International Conference on Parallel Architectures and Compilation Techniques (PACT), Seattle, WA, September 2019
(Acceptance rate: 36/126 = %28.6)
Ashutosh Pattnaik, Xulong Tang, Onur Kayiran, Adwait Jog, Asit Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita R. Das
Opportunistic Computing in GPU Architectures,
In the Proceedings of The 46th International Symposium on Computer Architecture (ISCA), Phoenix, AZ, June 2019
(Acceptance rate: 62/365 = %17.0)
Xulong Tang, Ashutosh Pattnaik, Onur Kayiran, Adwait Jog, Mahmut T. Kandemir, Chita R. Das
Quantifying Data Locality in Dynamic Parallelism in GPUs
In the Proceedings of the ACM on Measurement and Analysis of Computing Systems (POMACS) and
The ACM SIGMETRICS 2019 (SIGMETRICS), Phoenix, AZ, June 2019
(Acceptance rate: 28/208 ≈ 13.4%)
Hongyuan Liu, Mohamed Ibrahim, Onur Kayiran, Sreepathi Pai, Adwait Jog
Architectural Support for Efficient Large-Scale Automata Processing,
In the Proceedings of The 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Fukuoka, Japan, October 2018
(Acceptance rate: 74/348 = %21.3)
Hyojong Kim, Ramyad Hadidi, Lifeng Nai, Hyesoon Kim, Nuwan Jayasena, Yasuko Eckert, Onur Kayiran, Gabriel H. Loh
CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems
In the ACM Transactions on Architecture and Code Optimization,
(TACO), October 2018
Jieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf, Natalie Enright Jerger, Gabriel H. Loh
Modular Routing Design for Chiplet-based Systems,
In the Proceedings of The 45th International Symposium on Computer Architecture (ISCA), Los Angeles, CA, June 2018
(Acceptance rate: 64/373 = %17.2)
Haonan Wang, Fan Luo, Mohamed Ibrahim, Onur Kayiran, Adwait Jog
Efficient and Fair Multi-programming in GPUs via Pattern-based Effective Bandwidth Management,
In the Proceedings of The 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Vienna, Austria, February 2018
(Acceptance rate: 54/260 = %20.8)
Anthony Gutierrez, Bradford Beckmann, Alexandru Dutu, Joseph Gross, John Kalamatianos, Onur Kayiran, Michael LeBeane, Matthew Poremba, Brandon Potter, Sooraj Puthoor, Mark Wyse, Jieming Yin, Akshay Jain, Tim Rogers, Xianwei Zhang, Matt Sinclair
Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level,
In the Proceedings of The 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA) - Industrial Track, Vienna, Austria, February 2018
Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes
In the Proceedings of The 44th International Symposium on Computer Architecture
(ISCA), Toronto, Canada, June 2017
(Acceptance rate: 54/322 = %16.8)
Xulong Tang, Ashutosh Pattnaik, Huaipan Jiang, Onur Kayiran, Adwait Jog, Sreepathi Pai, Mohamed Ibrahim, Mahmut T. Kandemir, Chita R. Das
Controlled Kernel Launch for Dynamic Parallelism in GPUs,
In the Proceedings of The 23rd IEEE Symposium on High Performance Computer Architecture (HPCA), Austin, TX, February 2017
(Acceptance rate: 50/224 = %22.3)
Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael Schulte, Mike Ignatowski, Indrani Paul, Brad Beckmann, Steven Reinhardt, William Brantley, Joseph Greathouse, Onur Kayiran, Matthew Poremba, Wei Huang, Arun Karunanithi, Greg Sadowski, Vilas Sridharan, Steven Raasch, Mitesh Meswani
Design and Analysis of an APU for Exascale Computing,
In the Proceedings of The 23rd IEEE Symposium on High Performance Computer Architecture (HPCA) - Industrial Track, Austin, TX, February 2017
Onur Kayiran, Adwait Jog, Ashutosh Pattnaik, Rachata Ausavarungnirun, Xulong Tang, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das
µC-States: Fine-grained GPU Datapath Power Management
In the Proceedings of The 25th International Conference on Parallel Architectures and Compilation Techniques
(PACT), Haifa, Israel, September 2016
(Acceptance rate: 31/139 ≈ 22.3%)
Ashutosh Pattnaik, Xulong Tang, Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Chita R. Das
Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities
In the Proceedings of The 25th International Conference on Parallel Architectures and Compilation Techniques
(PACT), Haifa, Israel, September 2016
(Acceptance rate: 31/139 ≈ 22.3%)
Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie
OSCAR: Orchestrating STT-RAM Cache Traffic for Heterogeneous CPU-GPU Architectures,
In the Proceedings of The 49th IEEE/ACM International Symposium on Microarchitecture (MICRO), Taipei, Taiwan, October 2016
(Acceptance rate: 61/288 ≈ 21.2%)
Reena Panda, Yasuko Eckert, Nuwan Jayasena, Onur Kayiran, Michael Boyer, Lizy K. John
Prefetching Techniques for Near-memory Throughput Processors
Proceedings of The 30th ACM International Conference on Supercomputing
(ICS), Istanbul, Turkey, June 2016
(Acceptance rate: 43/178 ≈ 24.2%)
Adwait Jog, Onur Kayiran, Ashutosh Pattnaik, Mahmut T. Kandemir, Onur Mutlu, Ravishankar Iyer, Chita R. Das
Exploiting Core Criticality for Enhanced GPU Performance
Proceedings of The 42nd ACM SIGMETRICS
(SIGMETRICS), Antibes Juan-les-Pins, France, June 2016
(Acceptance rate: 28/208 ≈ 13.4%)
[Slides]Jieming Yin, Onur Kayiran, Matthew Poremba, Natalie Enright Jerger, Gabriel H. Loh
Efficient Synthetic Traffic Models for Large, Complex SoCs,
Proceedings of The 22nd International Symposium on High Performance Computer Architecture (HPCA), Barcelona, Spain, March 2016
(Acceptance rate: 53/245 ≈ 21.6%)
[Slides]
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Mahmut T. Kandemir, Onur Mutlu
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance,
Proceedings of The 24th International Conference on Parallel Architectures and Compilation Techniques (PACT), San Francisco, CA, October 2015
(Acceptance rate: 38/179 ≈ 21.2%)
[Slides]
Adwait Jog, Onur Kayiran, Tuba Kesten, Ashutosh Pattnaik, Evgeny Bolotin, Niladrish Chatterjee, Stephen W. Keckler, Mahmut T. Kandemir, Chita R. Das,
Anatomy of GPU Memory System for Multi-Application Execution
Proceedings of The 1st International Symposium on Memory Systems
(MEMSYS), Alexandria, VA, October 2015
[Slides]Onur Kayiran, Nachiappan CN, Adwait Jog, Rachata Ausavarungnirun, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das,
Managing GPU Concurrency in Heterogeneous Architectures,
Proceedings of The 47th International Symposium on Microarchitecture (MICRO), Cambridge, UK, December 2014
(Acceptance rate: 53/273 ≈ 19.4%)
[Summary] [Slides] [Lightning Slides] [Poster]
Best Paper Nomination
Onur Kayiran, Adwait Jog, Mahmut T. Kandemir, Chita R. Das,
Neither More Nor Less: Optimizing Thread-level Parallelism for GPGPUs,
Proceedings of The 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT), Edinburgh, Scotland, September 2013
(Acceptance rate: 36/208 ≈ 17.3%)
[Slides]
Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravi Iyer, Chita R. Das,
Orchestrated scheduling and prefetching for GPGPUs
Proceedings of The 40th International Symposium on Computer Architecture
(ISCA), Tel Aviv, Israel, June 2013
(Acceptance rate: 56/288 ≈ 19.4%)
[Slides]Adwait Jog, Onur Kayiran, Nachiappan CN, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar Iyer, Chita R. Das,
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance
Proceedings of The 18th International Conference on Architectural Support for Programming Languages and Operating Systems
(ASPLOS), Houston, TX, March 2013
(Acceptance rate: 44/191 ≈ 23.0%)
[Slides]Patents
Preemptive cache management policies for processing units, US10303602B2
Method and apparatus for performing memory prefetching, US10310981B2
Prioritizing local and remote memory access in a non-uniform memory access architecture, US10838864
Mechanism for dynamic latency-bandwidth trade-off for efficient broadcasts/multicasts, US10938709
Mechanism for distributed-system-aware difference encoding/decoding in graph analytics, US11068458
Adaptive cache reconfiguration via clustering, US11360891
Temporal Link Encoding, US11398831
Memory access response merging in a memory hierarchy, US11403221
Memory request priority assignment techniques for parallel processors, US11507522
Talks
Design and Analysis of Large-Scale GPU Architectures
University of Rochester, December 2018
Challenges in Die-stacked GPU Architectures
The College of William and Mary, January 2017
Efficient Synthetic Traffic Models for Large, Complex SoCs at HPCA 2016
Managing GPU Concurrency in Heterogeneous Architectures at MICRO 2014
Neither More Nor Less: Optimizing Thread-level Parallelism for GPGPUs at PACT 2013
Experience
Researcher at AMD Research, December 2016 - present
Postdoc researcher at AMD Research, July 2015 - December 2016
Internship at AMD Research, January 2015 - June 2015
Internship at Samsung Information Systems America (SISA) R&D Center, June 2013 - August 2013
Press Coverage and External Articles
AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme, June 22, 2018
AMD Expands Exascale Vision at IEEE HPC Symposium, March 7, 2017
AMD Researchers Eye APUs For Exascale, February 28, 2017
AMD reveals a Exascale MEGA APU in a new academic paper, February 21, 2017
PhD Dissertation
Onur Kayiran,
Parallelism-aware Resource Management Techniques for Many-core Architectures,
Committee: Chita Das, Mahmut Kandemir, Yuan Xie, Kenneth Jenkins, Onur Mutlu
Technical Reports
Onur Kayiran, Adwait Jog, Mahmut T. Kandemir, Chita R. Das,
Neither More Nor Less: Optimizing Thread-level Parallelism for GPGPUs,
TR-CSE-2012-006, CSE-Penn State Tech Report, Sept 2012
[Bib]
Educational Background
PhD in Computer Science and Engineering, The Pennsylvania State University, August 2010 - August 2015
MSc in Computer Engineering, San Jose State University, August 2008 - May 2010
BSc in Electrical and Electronics Engineering, Middle East Technical University, August 2003 - January 2008
High School: Ankara Atatürk Anadolu Lisesi
Service
Co-chair for:
Program Committee Member for:
ICPP 2022
GPGPU 2022
YArch 2022, 2021, 2020, 2019
NAS 2021
PACT 2020
uArch 2020
MICRO SRC 2020
ICS 2019
HPCA Industrial Track 2019
NAS 2017
Min-Move 2017
External Review Committee Member for:
ISCA 2022
MICRO 2019
HPCA 2018
Reviewer for:
TACO
IEEE MICRO
CAL
TC
TPDS
TCAD
JPDC
FGCS
MICPRO
External reviewer for:
ICS 2016
HPCA 2014
MICRO 2012
PhD Committee Member
Memberships
Other
Enjoys tennis, snooker, playing the drums and the guitar, history and cooking
Links