Onur Kayıran's Homepage

 

Onur Kayıran

Email : onur.kayiran@amd.com
Link to my Google Scholar Profile

About

I am an MTS Design Engineer at AMD Research. I completed my Ph.D. studies in Department of Computer Science and Engineering at The Pennsylvania State University, in 2015, where I worked with Chita R. Das and Mahmut T. Kandemir in High Performance Computing Lab.

Research Interests

Broadly, my research interests are in the area of computer architecture. Specifically, I work in GPU architectures, CPU-GPU heterogeneous architectures, interconnection networks, and die-stacking.

Publications

Talks

Design and Analysis of Large-Scale GPU Architectures

Challenges in Die-stacked GPU Architectures

Efficient Synthetic Traffic Models for Large, Complex SoCs at HPCA 2016

Managing GPU Concurrency in Heterogeneous Architectures at MICRO 2014

Neither More Nor Less: Optimizing Thread-level Parallelism for GPGPUs at PACT 2013

Experience

Press Coverage and External Articles

PhD Dissertation

Technical Reports

Educational Background

Service

Memberships

Other

Links

Google Scholar
LinkedIn
DBLP